In the semiconductor industry, it is common practice to perform certain tests on integrated circuits (ICs) in order to verify the integrity of the ICs. One type of test commonly performed is continuity testing which seeks to identify integrated circuits in which one or more of the pins do not have electrical continuity with the underlying circuit, i.e., there is an open circuit on one or more I/Os. (For ease discussion, the term I/O and pin will be used interchangeably to refer to any input node whether it takes the form of a pin or a ball or a pad or has any other configuration, and irrespective of whether it is a signal input or output or a power supply pin or ground pin.) The continuity test is performed using a test device commonly referred to as ATE, which either sources or sinks current to the pins being tested and provides a return path via one or more ground pins. In the absence of a fault condition, the ATE should detect a voltage at an I/O pin of about one diode drop, i.e. approximately 0.7 V. If, however, there is an open circuit on the I/O, the ATE, which acts like a current source will seek to supply the current (or sink the current) and thus register a substantial increase in voltage at the I/O.
As ICs have grown in function in performance over the years, the I/O count has also increased significantly. As a result different packaging formats have evolved for the ICs, including, for example, multi-row and column inline packages like high-pin-count Leadless Lead-frame Packages (LLP); Ball Grid Arrays (BGA) which are high density packages with I/O pins or contacts in the form of balls arranged in a matrix on the underside of the package, and micro Surface Mount Devices (micro SMD) which do not include a housing or package but include I/O contacts directly on the underside of the exposed die in the form of a matrix.
In order to make the continuity testing of such high I/O count ICs more efficient, one conventional method of testing involves continuity testing in parallel for all pins. This involves supplying current to all pins other than ground pins simultaneously and connecting the ground pins to ground to act as current return.
A high voltage (above or below a predefined level relative to a diode drop) on any of the pins indicates an open circuit and therefore a defective IC.
In fact, the ATE resource can also be used to detect a short circuit on any of the pins. For instance if any pin is internally short circuited, the ATE resource supplying the current would register a drop in voltage. Instead of a diode drop (diode turn on voltage) being measured by the ATE resource, it would measure essentially 0 V at the shorted out pin.
However, if a short occurs between two pins, the situation becomes more difficult. In such a situation, the parallel continuity test described above would be able to detect a defect only if the short causes the I/O voltage to swing away from a typical diode drop voltage. If, however, the short between two I/Os has an insignificant effect on the measured diode drop voltage, the parallel continuity test will not be able to detect the defect.
One approach used in the past to deal with this problem was to make use of other parametric or functional tests. In an IC where there are functional differences between different I/Os, parametric or functional tests can detect shorts to adjacent I/Os. However, such tests often become ineffective as the IC matures and as more layers are added that compound the functionality and make such indirect testing difficult or even impossible. Also, if the functionality or parameters of adjacent I/Os is similar, e.g., if two adjacent I/Os define the output channels of two separate but similar voltage regulators with similar output parameters, a short between the two I/Os may not be detected using such parametric or functional tests.
There is therefore a need for efficiently testing ICs for shorts between adjacent I/Os, especially in high I/O count devices.